Data buffer for programmable memory

ABSTRACT

A memory buffer and method are provided that interface input/output buffers and sense amplifiers of a multi-state programmable memory and sense amplifiers. The memory buffer includes switch circuits that are respectively placed between the input/output buffers and data register array and between the sense amplifiers and the data register array to read and write data in the memory regardless of volume and processing speed of the data. A controller controls the switch circuits to simultaneously operating the data transmission between the input/output buffers and the data buffer and between the sense amplifiers and the data buffer.

[0001] This application is a continuation of Ser. No. 09/185,088 filedNov. 3, 1998.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a data buffer and method, and inparticular, to a data buffer and method for using same that interfacesinput/output buffers in a multi-state programmable memory.

[0004] 2. Background of the Related Art

[0005] Generally, programmable memory devices such as a mass storageflash memory have less than 8(i.e., 1byte) input/output pins, andinternally have dozens of sense amplifiers. The input/output pinstransmit data by being synchronized to a clock signal, which has a clockcycle being dozens of nanoseconds (nsecs). The input/output buffercontinuously transmits a predetermined volume of data according to theclock cycle or clock signal speed. However, a time for the senseamplifier to read data from flash memory cells is dozens of nsecs, and atime for the sense amplifier to write the data to the flash memory cellsis hundreds of nsecs-dozens of microseconds (μsecs). Thus, both the datareading and the data writing speed are slower than the data processingspeed of the input/output pins. Accordingly, a data buffer is requiredto buffer differences of volume of data and of data transmission speedduring the data reading and the data writing processes.

[0006] A capacity of the data buffer should be equal to a minimum volumeof data that the data pins continuously receive. Generally, the minimumvolume of received data is equal to data in a row of a memory. An accesstime of the data buffer should be faster than a data transmission timeof the input/output buffer. The data buffer serves as an embedded memoryprovided in the programmable memory and mainly employs a latch array ora CMOS SRAM array, etc. therefor.

[0007]FIG. 1 is a circuit diagram of a related art data buffer for amulti-state programmable memory. As shown in FIG. 1, the related artdata buffer for the multi-state programmable memory is provided with acell array 1 having a plurality of columns, a plurality of senseamplifiers 2 that are respectively connected to a corresponding one ofthe columns of the cell array 1 and a plurality of data registers 3 eachhaving a couple of inverters, for example INV3-1A, INV3-1B. Theinverters INV3-1A and INV3-1B have inputs and outputs respectivelyconnected to each other to latch a corresponding one of the senseamplifiers 2. An input/output buffer 4 is connected to each output ofthe data registers 3.

[0008] As described above, the related art data buffer has variousdisadvantages. When the construction of the sense amplifiers is simple,each column of the programmable memory can be connected to acorresponding one of the sense amplifiers 2. Thus, each of the senseamplifiers 2 is connected to a latch, which is a corresponding one ofthe data registers 3, to serve as the data buffer. However, if the sizeof each of the sense amplifiers is so large that each column can not beconnected to the sense amplifiers, it is very difficult or impossible toarray the latches. Also, the data buffer for the multi-stateprogrammable memory should process data of at least 2 bits from thesense amplifiers. However, the related art data register has a problemprocessing the two or more bit data in a multi-state programmablememory.

[0009] The above references are incorporated by reference herein whereappropriate for appropriate teachings of additional or alternativedetails, features and/or technical background.

SUMMARY OF THE INVENTION

[0010] An object of the invention is to solve at least the aboveproblems and/or disadvantages and to provide at least the advantagesdescribed hereinafter.

[0011] Another object of the present invention is to provide a databuffer and method that substantially obviates one or more problems arecaused by limitations and disadvantages of the related art.

[0012] Another object of the present invention is to provide a databuffer that effectively processes data in a multi-state programmablememory regardless of volume and processing speed of the data and amethod for using same.

[0013] Another object of the present invention is to provide a databuffer and method for a multi-state programmable memory that selectivelycouples data in a multi-state memory cell to input/output terminals.

[0014] To achieve at least these objects and other advantages in a wholeor in parts and in accordance with the purpose of the present invention,as embodied and broadly described, a data buffer for a multi-stateprogrammable memory includes a sense amplifier formed in a plurality ofcolumns for temporarily storing data, a data register array configuredas the number of input/output buffer pins, each array has rowscorresponding to the number of cells to be processed by each senseamplifier, a plurality of upper read/write circuits connected betweenthe data register array and the input/output buffers, a plurality oflower read/write circuits connected between the data register array andthe sense amplifiers, an upper and a lower switch circuits forconnecting the data register array to the upper read/write circuits andto the lower read/write circuits, respectively, and a decoder having aplurality of outputs to select a plurality of wordlines of the dataregister array.

[0015] To further achieve the above objects in a whole or in parts, amethod for accessing in a page mode data of a multi-state programmablememory having a matrix of memory cells, data of the memory cells beingaccessed using a buffer and a sense amplifier via a data register arraystoring a plurality of data pages, according to the present invention isprovided that includes receiving data in a first page of the dataregister array from at least one of the buffer and the sense amplifierin a page mode and concurrently transmitting data from a second page ofthe data register array to at least one of the input/output buffer andthe sense amplifier in the page mode.

[0016] To further achieve the above objects in a whole or in parts, amethod for accessing a multi-state programmable memory using a databuffer according to the present invention is provided that includeswriting data to a first page of a first data register array selected bya first switch circuit using a first read/write circuit at a senseamplifier clock speed, transmitting the data from the first page to abuffer selected by a second switch circuit using a second read/writecircuit at a buffer clock speed and concurrently writing data to asecond page of the register array selected by the first switch circuitusing the first read/write circuit at the sense amplifier clock speedand transmitting the data from the second page selected by the secondswitch circuit to the buffer at the buffer clock speed.

[0017] Additional advantages, objects, and features of the inventionwill be set forth in part in the description which follows and in partwill become apparent to those having ordinary skill in the art uponexamination of the following or may be learned from practice of theinvention. The objects and advantages of the invention may be realizedand attained as particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The invention will be described in detail with reference to thefollowing drawings in which like reference numerals refer to likeelements wherein:

[0019]FIG. 1 a circuit diagram showing a related art data buffer for amulti-state programmable memory;

[0020]FIG. 2 is a circuit diagram showing a preferred embodiment of adata buffer for a multi-state programmable memory according to thepresent invention;

[0021]FIG. 3 is a circuit diagram showing an exemplary data registerarray of FIG. 2;

[0022]FIG. 4is a circuit diagram showing another preferred embodiment ofa data buffer for a multi-state programmable memory according to thepresent invention; and

[0023]FIG. 5 is a diagram showing an exemplary read/write circuit ofFIG. 4.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0024]FIG. 2 is a circuit diagram showing a first preferred embodimentof a data buffer for a multi-state programmable memory according to thepresent invention. As shown in FIG. 2, the data buffer for themulti-state programmable memory includes a register array 10 fortemporarily storing data to be processed by input/output buffers andsense amplifiers, a plurality of upper and a plurality of lowerread/write circuits 20-1, 20-2 respectively coupled to the input/outputbuffers and the sense amplifiers for reading and writing the data, andan upper switch circuit 30-1 and a lower switch circuit, 30-2 forcoupling the register array 10 to the upper and lower read/writecircuits 20-1, 20-2, respectively. A decoder 40 drives wordlines of theregister array 10. A counter 50 drives the decoder 40, and a controller60 couples the counter 50 to various clocks to receive and transmit thedata at an adequate speed. The controller 60 further selectively drivesthe upper and lower read/write circuits 20-1, 20-2.

[0025] As shown in FIG. 3, the register array 10 includes a plurality ofmatrix-type (e.g., L*Y) data register cells (10-1). Each of theplurality of matrix-type data register cells 10-1 includes NMOStransistors NM1, NM2, respectively having a gate coupled to a wordlineand a drain coupled to a bitline, and inverters INV1, INV2. Theinverters INV1, INV2 have inputs and outputs coupled to each other andcoupled between sources of the NMOS transistors NM1, NM2.

[0026] Operations of the first preferred embodiment of the data bufferfor the multi-state programmable memory according to the presentinvention will now be described. The controller 60 supplies clocksignals having different clock frequencies to the counter 50 inaccordance with a data transmission mode to the input/output buffers andwith a data transmission mode to the sense amplifiers. The controller 60selects the upper and lower switch circuits by mode, to drive the upperand lower read/write circuits 20-1, 20-2. Each sense amplifier iscoupled to a respective one of the read/write circuits 20-2, and aninput/output of each sense amplifier is in accordance with the operationcycle of the sense amplifier. The read/write circuits 20-1 coupled tothe input/output buffers are respectively synchronized with eachoperational clock signal and continuously input/output data by 1 bit.

[0027] The data register array 10 preferably reads data in a memory cellby three steps. First, the lower read/write circuit 20-2 writes data inaccordance with a sensing speed of the sense amplifier to a first pageof the register array 10 selected by the lower switch circuit 30-2.Second, the data written in the first step are transmitted from thefirst page, which is selected by the upper switch circuit 30-1, to theinput/output buffer by being synchronized with a clock signal of theinput/output buffer. Simultaneously, the lower read/write circuit 20-2writes data in accordance with the sensing speed of the sense amplifierto a second page of the register array 10. Third, the data written inthe second step are transmitted from the second page selected by theupper switch circuit 30-1 to the input/output buffer by beingsynchronized with a clock signal of the input/output buffer. In thesecond and third step, the data is continuously transmitted to theinput/output buffer.

[0028] With these three steps, information in one row of the memory canbe read, and the information in the entire memory can be read byrepeating the above steps. Thus, data in multi-state programmable memorycan be effectively read, regardless of volume and processing speed ofdata. A write mode, that is a program mode, operates in the oppositedirection of the read mode of the register array 10.

[0029]FIG. 4 is a circuit diagram showing a second preferred embodimentof a data buffer for a multi-state programmable memory according to thepresent invention. The second preferred embodiment of the data bufferfor the multi-state programmable memory includes a plurality of dataregister arrays 100, read/write circuits 200-1, 200-2, switch circuits300-1, 300-2, decoders 400 and counters 500.

[0030] As shown in FIG. 4, the plurality of data register arrays 100each has a plurality of columns for temporarily storing data and rows tobe processed by each sense amplifier, preferably formed as a number ofpins of input/output buffers. A read/write circuit 200-1 is coupledbetween the data register arrays 100 and an input/output buffer. Aread/write circuit 200-2 is coupled between the data register arrays 100and the sense amplifiers. Upper and lower switch circuits 300-1, 300-2respectively couple the data register arrays 100 to the read/writecircuits 200-1, 200-2. The decoders 400-1, 400-2 drive correspondingwordlines of the data register arrays 100, and the counters 500-1, 500-2drive the decoders 400-1, 400-2, respectively. The control circuit 600drives the decoders 400-1,400-2 by selecting two among clock signals andselectively coupling the data register arrays 100 to the read/writecircuits 200-1, 200-2.

[0031] As shown in FIG. 5, each of the read/write circuits 200-1, 200-2preferably includes an inverter INV301 for inverting an input datasignal DIN and switch NMOS transistors NM301, NM302. The switchtransistors NM301 and MN302 have gates that are commonly coupled, drainsthat are respectively coupled to a ground voltage VSS and sources thatare respectively coupled to the inverter INV301 and the input datasignal DIN. Register NMOS transistors NM303, NM304 each have a sourceand a gate coupled together, and a drain that receives an externalvoltage. Second and first PMOS transistors PM302, PM301 have sourcesthat respectively receive an external voltage VCC and gates that arecoupled together. A drain of the first PMOS transistor PM301 is coupledto the common gate. Mirror NMOS transistors NM305, NM306 have drainsrespectively coupled to the drains of the first and second PMOStransistors PM301, PM302, gates respectively coupled to the sources ofthe register NMOS transistors NM303, NM304 and sources coupled together.A bias NMOS transistor NM307 has a drain coupled to the common source ofthe mirror NMOS transistors NM305, NM306, a source coupled to the groundvoltage VSS and a gate that receives a bias voltage VBIAS.

[0032] The data buffer according to the second preferred embodiment ofthe present invention simultaneously transmits and receives data to/fromboth sides of the input/output buffers and the sense amplifiers. Sincethe data register array is divided into two pages that are controlled byseparate wordlines, one page transmits the data to the input/outputbuffers while the other page transmits the data to the sense amplifiers.

[0033] Therefore, the second preferred embodiment of a data bufferaccording to the present invention can interface the input/outputbuffers in the multi-state programmable memory that includes senseamplifiers, buffer the differences of the processing speed and thevolume of data, and voluntarily read and write data in the data registerarray. Further, the second preferred embodiment of the data bufferenables simultaneous data transmission between the input/output buffersand the data buffer and data transmission between the sense amplifiersand the data buffer.

[0034] The foregoing embodiments and advantages are merely exemplary andare not to be construed as limiting the present invention. The presentteaching can be readily applied to other types of apparatuses. Thedescription of the present invention is intended to be illustrative, andnot to limit the scope of the claims. Many alternatives, modifications,and variations will be apparent to those skilled in the art. In theclaims, means-plus-function clauses are intended to cover the structuresdescribed herein as performing the recited function and not onlystructural equivalents but also equivalent structures.

What is claimed is:
 1. A data buffer for a semiconductor device,comprising: a buffer; a sense amplifier coupled to a memory having cellsin a matrix form of rows and columns for reading and writing data to thememory; a first data register array coupled between the buffer and thesense amplifier, wherein the first data register array at least one of(1) stores second data received from the buffer into a second dataregion of the first data register and concurrently transmits storedfirst data from a first data region of the first data register array tothe sense amplifier, and (2) stores fourth data received from the senseamplifier in the second data region and concurrently transmits storedthird data from the first data region to the buffer, wherein the firstand second data regions each have plurality of cells are arranged in amatrix form of rows and columns; a control circuitry coupled to thefirst data register array, the control circuitry dividing the first dataregister array into the first and second data register regions; and afirst decoder circuit connected between the control circuitry and thefirst data register array that selects a corresponding row of the rowsin each of the first and second data regions such that data isrespectively read and written into the selected rows of data registercells in the corresponding first and second data regions.
 2. The databuffer of claim 1 , wherein the data is read from a first data page andwritten to a second data page.
 3. The data buffer of claim 1 , whereinprevious data stored by the sense amplifier is read from a first datapage by the buffer, and wherein current data is stored by the senseamplifier to a second data page.
 4. The data buffer of claim 1 , furthercomprising a second data register array and a second decoder.
 5. Thedata buffer of claim 1 , wherein the control circuitry comprises: afirst read/write circuit connected to the buffer; a first switch circuitconnected between the first read/write circuit and the first dataregister array; a second read/write circuit connected to the senseamplifier; and a second switch circuit connected between the first dataregister array and the second read/write circuit.
 6. The data buffer ofclaim 5 , wherein the second read/write circuit operates with a senseamplifier clock speed and the first read/write circuit operates at abuffer clock speed.
 7. The data buffer of claim 5 , wherein eachread/write circuit comprises: a logic-gate that logically processes aninput data signal; a first pair of switch transistors coupled to thelogic-gate and the input data signal, respectively; a pair of registertransistors receiving a first prescribed voltage that are respectivelycoupled to the first pair of switch transistors; a second pair of switchtransistors coupled to the first prescribed voltage; a pair of mirrortransistors having control electrodes respectively coupled to theregister transistors, second electrodes respectively coupled to thesecond switch transistors, and first electrodes coupled together at anode; and a bias transistor coupled to the node and having a controlelectrode that receives a bias voltage.
 8. The data buffer of claim 5 ,wherein each read/write circuit comprises: a logic-gate that logicallyprocesses an input data signal; a first pair of transistors havingcontrol electrodes that are commonly connected to a control signal,second electrodes respectively connected to a first prescribed voltage,and first electrodes connected to said logic-gate and said input datasignal, respectively; a second pair of transistors each of which has acontrol and first electrode connected together and to the firstprescribed voltage, and a second electrode that receives a secondprescribed voltage; a third pair of transistors having first electrodesthat respectively receive the second prescribed voltage and controlelectrodes that are connected together, and wherein a second electrodeof the third pair of transistors is coupled to the commonly coupledcontrol electrodes; a fourth pair of transistors having secondelectrodes respectively connected to the second electrodes of the thirdpair of transistors, and control electrodes that connected to the firstelectrodes of the second pair of transistors, respectively, and firstelectrodes connected to each other; and a bias transistor having asecond electrodes connected to the common first electrodes of the fourthpair transistors, a first electrode connected to the first prescribedvoltage and a control electrode that receives a bias voltage.
 9. Thedata buffer of claim 1 , wherein said each of the data register cellscomprises: first and second transistors, respectively having a controlelectrode coupled to a wordline and a second electrode coupled to abitline; and first and second logic gates having inputs and outputscoupled together and to corresponding ones of first electrodes of thefirst and second transistors.
 10. The data buffer of claim 1 , whereinthe first data register array has a plurality of wordlines correspondingto the rows, wherein the first decoder has a plurality of outputscorresponding to the wordlines to select the selected row.
 11. A methodfor accessing data of a multi-state programmable memory having a matrixof memory cells, data of the memory cells being accessed using a bufferand a sense amplifier via a data register array storing a plurality ofdata pages, the method comprising: receiving data in a first page of thedata register array from at least one of the buffer and the senseamplifier; and concurrently transmitting data from a second page of thedata register array to the other of said at least one of theinput/output buffer and the sense amplifier.
 12. The method of claim 11, further comprising decoding an address to select a row such that theselected row of the first and second page are written and read,respectively.
 13. The method of claim 11 , wherein the concurrentlytransmitted data from the second page transfers at a clock speed of thebuffer, and wherein the received data in the first page transfers at aclock speed of the sense amplifier.
 14. A method for accessing amulti-state programmable memory using a data buffer, wherein the databuffer has a prescribed number of I/O terminals and where theprogrammable memory includes a cell array having a matrix form of memorycells at intersections where wordlines cross bitlines, a wordline drivercoupled to the wordlines, and a decoder coupled to the bitlines,comprising: connecting the data buffer to a first read/write circuit;connecting the first read/write circuit to a first switch circuit;selectively connecting the first switch circuit to a first data registerarray that includes a first and second data pages each having cell arraywith a matrix form of rows and columns; selectively connecting a secondswitch circuit to the first data register array; connecting a secondread/write circuit to the second switch circuit; connecting an array ofsense amplifiers to the second read/write circuit; connecting thebitlines of the cell array to corresponding ones of the senseamplifiers; connecting a first decoder circuit to the first dataregister array; writing data received from the cell array to a firstpage of the first data register array selected by the second switchcircuit using the second read/write circuit at a sense amplifier clockspeed; transmitting the data from the first page to the data bufferselected by the first switch circuit using the first read/write circuitat a buffer clock speed and concurrently writing data to a second pageof the first data register array selected by the second switch circuitusing the second read/write circuit at the sense amplifier clock speed;and outputting the data from the second page selected by the firstswitch circuit to the buffer at the buffer clock speed.
 15. The methodof claim 14 , wherein the memory comprises a second data register array,wherein the first data page is in the first data register array and thesecond data page is in the second data register array.
 16. The method ofclaim 14 , further comprising: writing data received from the buffer tothe first page of the first data register array selected by the firstswitch circuit using the first read/write circuit at a buffer clockspeed; transmitting the data from the data from the first page to thesense amplifier selected by the second switch circuit using the secondread/write circuit at a sense amplifier clock speed to the senseamplifiers for transmission to the cell array and concurrently writingdata to the second page of the first data register array selected by thefirst switch circuit using the first read/write circuit at the bufferclock speed; and writing the data from the second page selected by thesecond switch circuit using the second read/write circuit to the senseamplifier, at the sense amplifier speed.
 17. The method of claim 14 ,wherein the data are temporarily stored in the first page and secondpage, and wherein the transmitting is repeatedly performed byalternating selection by the first and second switches, respectively, ofthe first and second pages.
 18. The method of claim 16 , wherein thedata are temporarily stored in the first page and second page, andwherein the transmitting is repeatedly performed by alternatingselection by the first and second switches, respectively, of the firstand second pages.
 19. A data buffer for a semiconductor device,comprising: an input/output buffer; a first read/write circuit connectedto the buffer; a first switch circuit connected to the first read/writecircuit; a first data register array connected to first switch circuit,wherein the first data register array is arranged in a matrix form ofrows and columns; a second switch circuit connected to the first dataregister array; a second read/write circuit connected to the secondswitch circuit; a sense amplifier that includes a plurality of sensingamplifiers each coupled to a corresponding bitline; a memory arrayconnected to the sense amplifier array that comprises, a cell arrayhaving a matrix form of memory cells at intersections where wordlinescross the bitlines, a wordline driver coupled to the wordlines, and abitline decoder coupled to the bitlines; a first decoder circuit coupledto the first data register array that selects a corresponding row suchthat data is read and written into the selected row of data registercells in a corresponding data region; and a controller coupled to thedecoder, the read/write circuits and the switches, wherein in a firstmode of operation, data from the buffer is alternately stored in firstand second regions of the first data register array at a buffer clockspeed and concurrently the data is alternately output from the secondand first regions, respectively, of the first data register at a senseamplifier clock speed.
 20. The data buffer of claim 19 , wherein in asecond mode of operation, data from the memory array is alternatelystored in the first and second regions, respectively, at the senseamplifier speed, and concurrently the data is alternately output fromthe second and first regions, respectively, at the data buffer clockspeed.
 21. The data buffer of claim 20 ,wherein the second read/writecircuit operates with the sense amplifier clock speed and the firstread/Write circuit operates at the buffer clock speed.
 22. The databuffer of claim 19 , wherein each read/write circuit comprises: a firstpair of transistors having control electrodes that are commonlyconnected to a control signal, second electrodes respectively connectedto a first prescribed voltage, and first electrodes connected to saidinput data signal, respectively; a second pair of transistors each ofwhich has a control and first electrode connected together and to thefirst prescribed voltage, and a second electrode that receives a secondprescribed voltage; a third pair of transistors having first electrodesthat respectively receive the second prescribed voltage and controlelectrodes that are connected together, and wherein a second electrodeof the third pair of transistors is coupled to the commonly coupledcontrol electrodes; a fourth pair of transistors having secondelectrodes respectively connected to the second electrodes of the thirdpair of transistors, and control electrodes that connected to the firstelectrodes of the second pair of transistors, respectively, and firstelectrodes connected to each other; and a bias transistor having asecond electrodes connected to the common first electrodes of the fourthpair transistors, a first electrode connected to the first prescribedvoltage and a control electrode that receives a bias voltage.
 23. Aread/write circuit for a data buffer comprising: a logic-gate thatlogically processes an input data signal; a first pair of transistorshaving control electrodes that are commonly connected to a controlsignal, second electrodes respectively connected to a first prescribedvoltage, and first electrodes connected to said logic-gate and saidinput data signal, respectively; a second pair of transistors each ofwhich has a control and first electrode connected together and to thefirst prescribed voltage, and a second electrode that receives a secondprescribed voltage; a third pair of transistors having first electrodesthat respectively receive the second prescribed voltage and controlelectrodes that are connected together, and wherein a second electrodeof the third pair of transistors is coupled to the commonly coupledcontrol electrodes; a fourth pair of transistors having secondelectrodes respectively connected to the second electrodes of the thirdpair of transistors, and control electrodes that connected to the firstelectrodes of the second pair of transistors, respectively, and firstelectrodes connected to each other; and a bias transistor having asecond electrodes connected to the common first electrodes of the fourthpair transistors, a first electrode connected to the first prescribedvoltage and a control electrode that receives a bias voltage.